1. Field of the Invention
The present invention relates to a semiconductor storage device such as dynamic random access memory (DRAM) in which a plurality of capacitor-type memory cells forms a memory cell array.
2. Description of the Related Art
FIG. 1 shows a circuit structure of a conventional semiconductor storage device. As shown in FIG. 1, bit information is held in memory cells ML and MR in a DRAM semiconductor storage device. In a RAS (Row Address Strobe) operation in this semiconductor storage device, the level of a selected word line, e.g., WL1, is set to a VPP (“high”) level, and a charge is discharged to a bit line BL from the memory cell MR that is connected to the word line WL1. In this case, a relatively large potential difference ΔV must be created by the discharged charge between the bit line BL and a bit line BLb in order for the potential difference ΔV to be detected by a sense amplifier SA. An example of a known method for achieving this involves using a transfer gate TG1 to temporarily break the connection between the sense amplifier SA and the memory cell ML on the side of the word line WL0 that was not selected.
However, due to the load capacitance of the bit line BL connected to the memory cell across the transfer gate TG2, when the sense amplifier performs a sensing operation and amplifies ΔV, problems occur in that time is required for the bit line BL to be set to the VDDA (bit information retention potential) level, and for the bit line BLb to be set to the VSS (ground) level. The peak current is also increased by charging and discharging of the bit line BL at the time of sense latching, the sense amplifier power supply cannot adapt, and there is a precipitous drop from the VDDA level as the power supply voltage that must be supplied. For example, as shown in FIG. 2, the potential of the sense amplifier power supply SLP falls from the VDDA level at the start of sense latching.
A method for addressing these problems involves setting a TGR signal inputted to the transfer gate on the side of the memory cell MR to the VDDA level only at the start of sense latching, whereby the transfer gate TG2 connected to the memory cell MR is placed in the OFF state, and the load capacitance on the side of the memory cell MR is withdrawn from the sense amplifier SA only at the start of sense latching. The potential of the bit line BL on the side of the sense amplifier across the transfer gate TG2 is thereby rapidly amplified to the VDDA level. A technique similar to this method is disclosed in Japanese Laid-open Patent Application No. 2003-168294.
However, as the load capacitance of memory cells has decreased in conjunction with recent process refinement and increased memory capacity, the number of memory cells to be connected to the bit lines has increased. Under these circumstances, the sense amplifier power supply cannot adapt to the peak current due to charging and discharging of the bit lines, and there is a more severe drop in the supplied power supply voltage. These problems result in increased amplification time of the sense amplifier, and access times are becoming difficult to reduce.
The present invention was contrived in view of the problems described above, and an object of the present invention is to provide a semiconductor storage device in which the access time can be reduced even when the process is refined and the memory capacity is increased.